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FPL
2010
Springer

Multiplicative Square Root Algorithms for FPGAs

8 years 11 months ago
Multiplicative Square Root Algorithms for FPGAs
Abstract--Most current square root implementations for FPGAs use a digit recurrence algorithm which is well suited to their LUT structure. However, recent computing-oriented FPGAs include embedded multipliers and RAM blocks which can also be used to implement quadratic convergence algorithms, very high radix digit recurrences, or polynomial approximation algorithms. The cost of these solutions is evaluated and compared, and a complete implementation of a polynomial approach is presented within the open-source FloPoCo framework. This polynomial approach allows a shorter latency and higher frequency than the digit recurrence approach, and improves over previous multiplicative approaches. However, the cost of IEEE-compliant correct rounding is shown to be very high.
Florent de Dinechin, Mioara Joldes, Bogdan Pasca,
Added 11 Feb 2011
Updated 11 Feb 2011
Type Journal
Year 2010
Where FPL
Authors Florent de Dinechin, Mioara Joldes, Bogdan Pasca, Guillaume Revy
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