Sciweavers

Share
DSD
2008
IEEE

Network Interface Sharing Techniques for Area Optimized NoC Architectures

9 years 4 months ago
Network Interface Sharing Techniques for Area Optimized NoC Architectures
Although preliminary analysis frameworks point out the performance speed-ups achievable by on-chip networks with respect to state-of-the-art interconnects, the area concern remains one of the most daunting challenges to make this interconnect technology mainstream. A common approach to relieve the problem consists of sharing most of network interface resources among a number of processor cores. However, buffering resources need to be replicated and control logic reaches a complexity that limits maximum achievable frequency. This paper proposes full sharing of network interface resources, including buffers, thus trading performance for area. While area improvements are significant, a number of physical and system-level effects might mitigate performance degradation, making our technique a promising solution for area efficient network-on-chip realizations across a range of operating conditions.
Alberto Ferrante, Simone Medardoni, Davide Bertozz
Added 29 May 2010
Updated 29 May 2010
Type Conference
Year 2008
Where DSD
Authors Alberto Ferrante, Simone Medardoni, Davide Bertozzi
Comments (0)
books