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IFIP
2001
Springer

A New Efficient VLSI Architecture for Full Search Block Matching Motion Estimation

12 years 1 months ago
A New Efficient VLSI Architecture for Full Search Block Matching Motion Estimation
: A new efficient type I architecture for motion estimation in video sequences based on the Full-Search Block-Matching (FSBM) algorithm is proposed in this paper. This architecture presents minimum latency, maximum throughput and full utilization of the hardware resources, combining both pipelining and parallel processing techniques. The implementation of an array processor for motion estimation in a single-chip using 0.25   m CMOS technology is presented. Experimental results show that this processor is able to estimate motion vectors in 4CIF video sequences at a rate of 16 frames/s. Key words: Motion Estimation, Block Matching, Array Architectures, Specialized Processors.
Nuno Roma, Leonel Sousa
Added 30 Jul 2010
Updated 30 Jul 2010
Type Conference
Year 2001
Where IFIP
Authors Nuno Roma, Leonel Sousa
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