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ACIVS
2005
Springer

Reduced-Bit, Full Search Block-Matching Algorithms and Their Hardware Realizations

10 years 5 months ago
Reduced-Bit, Full Search Block-Matching Algorithms and Their Hardware Realizations
Abstract. The Full Search Block-Matching Motion Estimation (FSBME) algorithm is often employed in video coding for its regular dataflow and straightforward architectures. By iterating over all candidates in a defined Search Area of the reference frame, a motion vector is determined for each current frame macroblock by minimizing the Sum of Absolute Differences (SAD) metric. However, the complexity of the method is prohibitively high, amounting to 6080% of the encoder’s computational burden, and making it unsuitable for many real-time video applications. One means of alleviating the problem is to calculate SAD values using fewer bits (Reduced-Bit SAD), however the reduced dynamic range may compromise picture quality. The current work presents an algorithm, which corrects the RBSAD to full resolution under appropriate conditions. Our results demonstrate that the optimal conditions for correction include a knowledge of the motion vectors of neighboring blocks in space and/or time.
Vincent M. Dwyer, Shahrukh Agha, Vassilios A. Chou
Added 26 Jun 2010
Updated 26 Jun 2010
Type Conference
Year 2005
Where ACIVS
Authors Vincent M. Dwyer, Shahrukh Agha, Vassilios A. Chouliaras
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