Non-scan design-for-testability of RT-level data paths

- This paper presents a non-scan design-for-testability technique applicable to register-transfer(RT) level data path circuits, which are usually very hard-to-test due to the presence of complex loop structures. We develop a new testability measure, and utilize the RT-level structure of the data path, for cost-effective re-design of the circuitto make it easily testable, without havingto eitherscanany flipflop or breakloops directly. The non-scanDFT technique was applied to several data path circuits. Experimental results demonstrate the feasibility of producing non-scan testable data paths, which can be tested at-speed. The hardware overhead and the test application time required for the non-scan designs is significantly lower than the corresponding partial scan designs.

• Type: Conference
• Year: 1994
• Where: ICCAD
• Authors: Sujit Dey, Miodrag Potkonjak
• Keywords: Data Path Circuits, Data Paths, Hardware, ICCAD 1994, Level Data Path