An Optimized Front-End Physical Register File with Banking and Writeback Filtering

In recent years, processor manufacturers have converged on two types of register file architectures. Both IBM with its POWER series and Intel with its Pentium series are using a central storage for all in-flight values, which offers a high performance potential. AMD, on the other hand, uses an optimized implementation of the Future File for its line of Opteron processors. Both approaches have limitations that may preclude there application in future processor implementations. The centralized register file scales poorly in terms of power-performance. The Future File may be limited by the requirement of distributed reservation stations and by the branch misprediction recovery scheme. This paper proposes to give processor designer teams another choice by combining a traditional future file architecture with the concept of a central physical register file. This new register file is used in the ”front end” in combination with value storage in the instruction queue. Further, it is...

• Type: Conference
• Year: 2004
• Where: PACS
• Authors: Miquel Pericàs, Rubén González, Adrián Cristal, Alexander V. Veidenbaum, Mateo Valero
• Keywords: Future File, Hardware, PACS 2004, Register file, Register file Architectures