Parallel FFT Algorithms on Network-on-Chips

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Parallel FFT Algorithms on Network-on-Chips
This paper presents several parallel FFT algorithms with different degree of communication overhead for multiprocessors in Network-on-Chip(NoC) environment. Three different methods of parallel FFT are presented. One is the reference parallel FFT for comparison, and the other two with well-distributed computation as well as reduced communication overhead. By evenly distributing parallel computation tasks which uses data locality, the execution time for completing each stage of FFT can be reduced. Moreover, by optimizing data exchanges we minimize the communication overhead. Depending on the communication regularity, one can select appropriate parallel FFT algorithm. By using the simulation results of our cycle-accurate SystemC NoC model with a parameterizable 2-D mesh architecture, and the performance analysis in time as well as complexity, our proposed algorithms are shown to outperform other parallel FFT algorithm or high-speed DSP implementations.
Jun Ho Bahn, Jungsook Yang, Nader Bagherzadeh
Added 31 May 2010
Updated 31 May 2010
Type Conference
Year 2008
Where ITNG
Authors Jun Ho Bahn, Jungsook Yang, Nader Bagherzadeh
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