A New Approach to Pipeline FFT Processor

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A New Approach to Pipeline FFT Processor
A new VLSI architecture for real-time pipeline FFT processor is proposed. A hardware oriented radix-22 algorithm is derived by integrating a twiddle factor decomposition technique in the divide and conquer approach. Radix-22 algorithm has the same multiplicative complexity as radix-4 algorithm, but retains the butterfly structure of radix-2 algorithm. The single-path delay-feedback architecture is used to exploit the spatial regularity in signal flow graph of the algorithm. For length-N DFT computation, the hardwarerequirementof the proposed architecture is minimal on both dominant components: log4 N 1 complex multipliers and N 1 complex data memory. The validity and efficiency of the architecture have been verified by simulation in hardware description language VHDL.
Shousheng He, Mats Torkelson
Added 07 Aug 2010
Updated 07 Aug 2010
Type Conference
Year 1996
Where IPPS
Authors Shousheng He, Mats Torkelson
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