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TRETS
2008

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Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations

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Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations

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N. Pete Sedcole, Peter Y. K. Cheung

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Added	15 Dec 2010
Updated	15 Dec 2010
Type	Journal
Year	2008
Where	TRETS
Authors	N. Pete Sedcole, Peter Y. K. Cheung

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