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2000
ACM

A performance optimization method by gate sizing using statistical static timing analysis

10 years 2 months ago
A performance optimization method by gate sizing using statistical static timing analysis
We propose a gate resizing method for delay and power optimization that is based on statistical static timing analysis. Our method focuses on the component of timing uncertainties due to local random fluctuation. Utilizing our method, over-design of a circuit can be eliminated and high-performance and high-reliability LSI design can be realized. The effectiveness of our method is examined by 6 benchmark circuits. We verify that our method can reduce delay and power dissipation from the circuits optimized without the consideration of fluctuation.
Masanori Hashimoto, Hidetoshi Onodera
Added 01 Aug 2010
Updated 01 Aug 2010
Type Conference
Year 2000
Where ISPD
Authors Masanori Hashimoto, Hidetoshi Onodera
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