pFPC: A Parallel Compressor for Floating-Point Data

This paper describes and evaluates pFPC, a parallel implementation of the lossless FPC compression algorithm for 64-bit floating-point data. pFPC can trade off compression ratio for throughput. For example, on a 4-core 3 GHz Xeon system, it compresses our

• Type: Conference
• Year: 2009
• Where: DCC
• Authors: Martin Burtscher, Paruj Ratanaworabhan
• Keywords: Computer Graphics, DCC 2009, GHz Xeon System, Lossless Fpc Compression