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2010
ACM

Physical synthesis of bus matrix for high bandwidth low power on-chip communications

10 years 9 months ago
Physical synthesis of bus matrix for high bandwidth low power on-chip communications
As the thermal wall becomes the dominant factor limiting VLSI circuit performance, and the interconnect wires become the primary power consumer, power efficiency of onchip data throughput is nowadays a critical target for SoC designers. Under this trend, bus matrices are mostly used in current system-on-chips (SoCs) because of their simplicity and good performance. We introduce a bus matrix synthesis flow to optimize on-chip communications, to keep the low delay of buses, reduce power by bus gating, and reduce wires by wire sharing. The proposed algorithms are able to help designers create high capability yet compact and efficient bus matrices for future low power SoCs. Categories and Subject Descriptors J.6 [Computer Applications]: Computer-aided design General Terms Algorithms, design, performance Keywords Bandwidth, power efficiency, wire efficiency
Renshen Wang, Evangeline F. Y. Young, Ronald L. Gr
Added 17 May 2010
Updated 17 May 2010
Type Conference
Year 2010
Where ISPD
Authors Renshen Wang, Evangeline F. Y. Young, Ronald L. Graham, Chung-Kuan Cheng
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