Physical synthesis of bus matrix for high bandwidth low power on-chip communications

As the thermal wall becomes the dominant factor limiting VLSI circuit performance, and the interconnect wires become the primary power consumer, power efficiency of onchip data throughput is nowadays a critical target for SoC designers. Under this trend, bus matrices are mostly used in current system-on-chips (SoCs) because of their simplicity and good performance. We introduce a bus matrix synthesis flow to optimize on-chip communications, to keep the low delay of buses, reduce power by bus gating, and reduce wires by wire sharing. The proposed algorithms are able to help designers create high capability yet compact and efficient bus matrices for future low power SoCs. Categories and Subject Descriptors J.6 [Computer Applications]: Computer-aided design General Terms Algorithms, design, performance Keywords Bandwidth, power efficiency, wire efficiency

• Type: Conference
• Year: 2010
• Where: ISPD
• Authors: Renshen Wang, Evangeline F. Y. Young, Ronald L. Graham, Chung-Kuan Cheng
• Keywords: Bus Matrices, Hardware, ISPD 2010, Low Power Socs, Power Efficiency