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2006
IEEE

Polaris: A System-Level Roadmap for On-Chip Interconnection Networks

9 years 8 months ago
Polaris: A System-Level Roadmap for On-Chip Interconnection Networks
Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the increasing on-chip communication demand among the computation elements necessitates the use of scalable, highbandwidth network-on-chip (NoC) fabrics. As transistor feature sizes are further miniaturized leading to rapidly increasing amounts of on-chip resources, more complicated and powerful NoC architectures become feasible that can support more sophisticated and demanding applications. Given the myriad emerging software-hardware combinations, for costeffectiveness, a system designer critically needs to prune this widening NoC design space to identify the architecture(s) that best balance(s) cost/performance, before the actual design process begins. This prompted us to develop Polaris1 , a system-level roadmap for on-chip interconnection networks that guides designers towards the most suitable network design(s) t...
Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin
Added 16 Mar 2010
Updated 16 Mar 2010
Type Conference
Year 2006
Where ICCD
Authors Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin Li, Li-Shiuan Peh
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