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2007
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Power reduction of chip multi-processors using shared resource control cooperating with DVFS

11 years 5 months ago
Power reduction of chip multi-processors using shared resource control cooperating with DVFS
This paper presents a novel power reduction method for chip multi-processors (CMPs) under real-time constraints. While the power consumption of processing units (PUs) on CMPs can be reduced without violating real-time constraints by dynamic voltage and frequency scaling (DVFS), the clock frequency of each PU cannot be determined independently because of the performance impact caused by the conflict for the shared resources. To minimize power consumption in this situation, we first derive an analytical model which provides the optimal priority and clock frequency setting, and then propose a method of controlling the priority of shared resource accesses in cooperation with DVFS. From the analytical model, in dual-core CMPs, we reveal that the total power consumption is minimized when the clock frequency of two PUs becomes the same. An experiment with a synthetic benchmark supports the validity of the analytical model and the evaluation results with real applications show that the propos...
Ryo Watanabe, Masaaki Kondo, Hiroshi Nakamura, Tak
Added 16 Aug 2010
Updated 16 Aug 2010
Type Conference
Year 2007
Where ICCD
Authors Ryo Watanabe, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya
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