Predicting memory-access cost based on data-access patterns

Improving memory performance at software level is more effective in reducing the rapidly expanding gap between processor and memory performance. Loop transformations (e.g. loop unrolling, loop tiling) and array restructuring optimizations improve the memory performance by increasing the locality of memory accesses. To find the best optimization parameters at runtime, we need a fast and simple analytical model to predict the memory access cost. Most of the existing models are complex and impractical to be integrated in the runtime tuning systems. In this paper, we propose a simple, fast and reasonably accurate model that is capable of predicting the memory access cost based on a wide range of data access patterns that appear in many scientific applications.

• Type: Conference
• Year: 2004
• Where: CLUSTER
• Authors: Surendra Byna, Xian-He Sun, William Gropp, Rajeev Thakur
• Keywords: CLUSTER 2004, Distributed And Parallel Computing, Memory Access Cost, Memory Accesses, Memory Performance