QOS Driven Network-on-Chip Design for Real Time Systems

Real Time embedded system designers are facing extreme challenges in underlying architectural design selection. It involves the selection of a programmable, concurrent, heterogeneous multiprocessor architecture platform. Such a multiprocessor system on chip (MPSoC) platform has set new innovative trends for the real-time systems and system on Chip (SoC) designers. The consequences of this trend imply the shift in concern from computation and sequential algorithms to modeling concurrency, synchronization and communication in every aspect of hardware and software co-design and development. With a billion transistors era, some of the main problems in deep sub-micron technologies characterized by gate lengths in the range of 60-90 nm arise from non scalable wire delays, errors in signal integrity and un-synchronized communication. These problems have been addressed by the use of packet switched Network on Chip (NOC) architecture for future SoCs and thus, real-time systems. Such a NOC base...

• Type: Conference
• Year: 2006
• Where: CCECE
• Authors: Ankur Agarwal, Mehmet Mustafa, Abhijit S. Pandya
• Keywords: CCECE 2006, Chip, Communication Backbone, Electrical And Computer Engineering, Turn Prohibition