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DAC
2006
ACM

Rapid estimation of control delay from high-level specifications

10 years 26 days ago
Rapid estimation of control delay from high-level specifications
We address the problem of estimating controller delay from high-level specifications during behavioral synthesis. Typically, the critical path of a synthesised behavioral design goes through both the datapath and the control logic; yet most scheduling algorithms account only for datapath and ignore control delay, leading to timing uncertainties in the resulting designs. We present an estimation technique for computing a fast, robust, scalable, and reasonably accurate approximation of the control delay from behavioral specifications. The delay estimate is formulated in terms of the properties of the input specification and other inputs to the synthesis process such as resource constraints. Categories and Subject Descriptors B.5.2 [Register-Transfer-Level Implementation]: Design Aids--Automatic synthesis General Terms Performance, Experimentation Keywords High Level Synthesis, FSM, Control Delay, Estimation
Gagan Raj Gupta, Madhur Gupta, Preeti Ranjan Panda
Added 13 Nov 2009
Updated 13 Nov 2009
Type Conference
Year 2006
Where DAC
Authors Gagan Raj Gupta, Madhur Gupta, Preeti Ranjan Panda
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