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2003
IEEE

Rapid Exploration of Pipelined Processors through Automatic Generation of Synthesizable RTL Models

9 years 5 months ago
Rapid Exploration of Pipelined Processors through Automatic Generation of Synthesizable RTL Models
As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. System architects critically need modeling techniques to rapidly explore and evaluate candidate architectures based on area, power, and performance constraints. We present an exploration framework for pipelined processors. We use the EXPRESSION Architecture Description Language (ADL) to capture a wide spectrum of processor architectures. The ADL has been used to enable performance driven exploration by generating a software toolkit from the ADL specification. In this paper, we present a al abstraction technique to automatically generate synthesizable RTL from the ADL specification. Automatic generation of RTL enables rapid exploration of candidate architectures under given design constraints such as area, clock frequency, power, and performance. Our exploration results demonstrate the power of reuse in comp...
Prabhat Mishra, Arun Kejariwal, Nikil Dutt
Added 05 Jul 2010
Updated 05 Jul 2010
Type Conference
Year 2003
Where RSP
Authors Prabhat Mishra, Arun Kejariwal, Nikil Dutt
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