Real-time implementation of H.263+ using TI TMS320c6201 digital signal processor

In this paper, we use a digital signal processor (DSP) to implement a real-time H.263+ codec. We use fast algorithms to reduce the codec computational complexity. Furthermore, the C programs are modified to take advantages of the DSP architecture and its C compiler features to reduce the on-chip memory and to increase the processing speed. In addition, a simple but effective ratecontrol algorithm is implemented to maintain the target bit rate. We can encode about 20 QCIF frames/second using one TI DSP. And the average decoding speed is about 26 QCIF frames/second.

• Type: Conference
• Year: 2003
• Where: ISCAS
• Authors: Timothy K. Shih, Chia-Yang Tsai, Hsueh-Ming Hang
• Keywords: Codec Computational Complexity, Digital Signal Processor, ISCAS 2003, Real-time H.263+ Codec