Redundant Adders Consume Less Energy

— We conduct a complete analysis of the effect of digit redundancy in adders on their delay, power, energy, and energy-delay product. To our knowledge, this is the first such detailed analysis. We discuss the hybrid signed digit representations that offer a continuum of choices from two’s complement representation on one extreme, all the way to a fully signed digit representation on the other extreme. Power and time delay reductions are achieved as a result of algorithmic level changes. Our analysis

• Type: Conference
• Year: 2006
• Where: APCCAS
• Authors: Kavallur Gopi Smitha, H. A. H. Fahmy, A. Prasad Vinod
• Keywords: APCCAS 2006, Digit Redundancy, Digit Representation, Hardware, Hybrid Signed Digit