APCCAS 2006 - PDF Preprint Papers

APCCAS 2006 Asia Pacific Conference on Circuits and Systems

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APCCAS
2006
IEEE

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An Active-RC Complex Filter with Mixed Signal Tuning System for Low-IF Receiver

13 years 10 months ago

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—An active-RC complex filter synthesized from leapfrog low-pass prototype is proposed in this paper, which is less sensitive to components values variation comparing with the com...

Dingkun Du, Yongming Li, Zhihua Wang, Seeteck Tan

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Id	Views	Title	Status

1	478	An Active-RC Complex Filter with Mixed Signal Tuning System for Low-IF Receiver	claim
2	373	A New High Precision Low Offset Dynamic Comparator for High Resolution High Speed ADCs	claim
3	364	An Analysis of THD in Class D Amplifiers	claim
4	323	Real-Time Implementation of a Particle Filter with Integrated Voice Activity Detector for Acoustic Speaker Tracking	claim
5	307	A Fast-Lock-In ADPLL with High-Resolution and Low-Power DCO for SoC Applications	claim
6	304	Low-Power Bus Transform Coding for Multilevel Signals	claim
7	296	2PADCL: Two Phase drive Adiabatic Dynamic CMOS Logic	claim
8	292	Two Novel Phase-Frequency Detectors	claim
9	292	Another Look at the Sequential Multiplier over Normal Bases	claim
10	290	An Improved Soft-Input CAVLC Decoder for Mobile Communication Applications	claim
11	272	Power Analysis for the MOS AC/DC Rectifier of Passive RFID Transponders	claim
12	271	Fully-multiplexed First-order 3D IIR Frequency-Planar Filter Module	claim
13	271	Leakage Optimized DECAP Design for FPGAs	claim
14	269	A Memory Bandwidth Optimized Interpolator for Motion Compensation in the H.264 Video Decoding	claim
15	268	A One-Dimensional Technique for Embedding Data in A JPEG Color Image	claim
16	267	VLSI Implementation of a 600-Mbps MIMO-OFDM Wireless Communication System	claim
17	264	FPGA-Based Design of a Pulsed-OFDM System	claim
18	261	Area/Delay Efficient Recoding Methods for Parallel CORDIC Rotations	claim
19	261	A Grouped Fast Fourier Transform Algorithm Design For Selective Transformed Outputs	claim
20	258	A 12-bit CMOS Current Steering D/A Converter for Embedded Systems	claim
21	256	Asynchronous Design Methodology for an Efficient Implementation of Low power ALU	claim
22	254	Redundant Adders Consume Less Energy	claim
23	254	Filterbank Framework for Multicarrier Systems with Improved Subcarrier Separation	claim
24	253	Design of Optimal Decimation and Interpolation Filters for Low Bit-Rate Image Coding	claim
25	252	A Display Order Oriented Scalable Video Decoder	claim
26	251	Design of a Dynamic PCM Selector for Non-deterministic Environment	claim
27	251	Implementation of a H.264 decoder with Template-based Communication Refinement	claim
28	249	Uncertainty Management for Estimation in Dynamical Systems	claim
29	247	Exploiting Chaos for Computation	claim
30	246	Digital Filter Design: Global Solutions via Polynomial Optimization	claim
31	245	Design of Time Domain Equalizers Incorporating Radio Frequency Interference Suppression	claim
32	245	Digital Audio Broadcasting System Modeling and Hardware Implementation	claim
33	242	Gramian-Preserving Frequency Transformation for State-Space Digital Filters	claim
34	241	A Fast Algorithm and Its Architecture for Motion Estimation in MPEG-4 AVC/H.264 Video Coding	claim
35	238	Semi-Blind Time Domain Equalization for MIMO-OFDM Systems	claim
36	233	Flexible Filter Bank Dimensioning for Multicarrier Modulation and Frequency Domain Equalization	claim
37	233	Jointly Optimized Modulated-Transmitter and Receiver FIR MIMO Filters	claim
38	229	Generation of Panoramic Image from Aerial Video utilizing JP2K Wavelet for River Surveillance	claim
39	229	Low Power Combinational Multipliers using Data-driven Signal Gating	claim
40	227	FPGA Prototyping of Spatio-temporal 2D IIR Broadband Beam Plane-wave Filters	claim
41	224	A High-Performance VLSI Architecture for Intra Prediction and Mode Decision in H.264/AVC Video Encoding	claim
42	224	A Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate and Its CAD Environment	claim
43	206	Low Power Pre-Comparison Scheme for NOR-Type 10T Content Addressable Memory	claim
44	206	On the Properties And Design of Stable IIR Transfer Functions Generated Using Fibonnaci Numbers	claim

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