Requirements and Concepts for Transaction Level Assertions

— The latest development of hardware design and ation methodologies shows a trend towards abstraction levels higher than RTL, referred to as transaction level (TL). Transaction level models are used for early prototyping and as reference models for the verification of their RTL representation. Hence, ensuring their quality is vital for the design process. Assertion based verification (ABV) has already given a good return of investment for RTL designs. We expect the same benefit from leveraging ABV on transaction level; however mapping RTL ABV methodology directly to TL poses severe problems due to raction of time and different model of computation. In this paper we present requirements for TL ABV and introduce a conceptual language for specifying TL properties. We use a simple application example for illustrating the concepts and outline a possible SystemC execution model of the conceptual language.

• Type: Conference
• Year: 2006
• Where: ICCD
• Authors: Wolfgang Ecker, Volkan Esen, Michael Hull, Thomas Steininger, Michael Velten
• Keywords: Hardware, ICCD 2006, RTL ABV Methodology, RTL Representation, TL ABV