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RTAS
1997
IEEE

Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches

9 years 8 months ago
Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
ÐWith effective packet-scheduling mechanisms, modern integrated networks can support the diverse quality-of-service requirements of emerging applications. However, arbitrating between a large number of small packets on a high-speed link requires an efficient hardware implementation of a priority queue. To highlight the challenges of building scalable priority queue architectures, this paper includes a detailed comparison of four existing approaches: a binary tree of comparators, priority encoder with multiple first-infirst-out lists, shift register, and systolic array. Based on these comparison results, we propose two new architectures that scale to the large number of packets (N) and large number of priority levels (P) necessary in modern switch designs. The first architecture combines the faster clock speed of a systolic array with the lower memory requirements of a shift register, resulting in a hybrid design; a tunable parameter allows switch designers to carefully balance the tra...
Sung-Whan Moon, Kang G. Shin, Jennifer Rexford
Added 06 Aug 2010
Updated 06 Aug 2010
Type Conference
Year 1997
Where RTAS
Authors Sung-Whan Moon, Kang G. Shin, Jennifer Rexford
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