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    RTAS
    1997
    IEEE
    176views Embedded Systems» more  RTAS 1997»
    Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
    13 years 8 months ago
    Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
    Download  www.cs.pitt.edu
    ÐWith effective packet-scheduling mechanisms, modern integrated networks can support the diverse quality-of-service requirements of emerging applications. However, arbitrating bet...
    Sung-Whan Moon, Kang G. Shin, Jennifer Rexford
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