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IEEEHPCS
2010

Scalable instruction set simulator for thousand-core architectures running on GPGPUs

8 years 8 months ago
Scalable instruction set simulator for thousand-core architectures running on GPGPUs
Simulators are still the primary tools for development and performance evaluation of applications running on massively parallel architectures. However, current virtual platforms are not able to tackle the complexity issues introduced by 1000-core future scenarios. We present a fast and accurate simulation framework targeting extremely large parallel systems by specifically taking advantage of the inherent potential processing parallelism available in modern GPGPUs.
Shivani Raghav, Martino Ruggiero, David Atienza, C
Added 26 Jan 2011
Updated 26 Jan 2011
Type Journal
Year 2010
Where IEEEHPCS
Authors Shivani Raghav, Martino Ruggiero, David Atienza, Christian Pinto, Andrea Marongiu, Luca Benini
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