Scalable power control for many-core architectures running multi-threaded applications

Optimizing the performance of a multi-core microprocessor within a power budget has recently received a lot of attention. However, most existing solutions are centralized and cannot scale well with the rapidly increasing level of core integration. While a few recent studies propose power control algorithms for many-core architectures, those solutions assume that the workload of every core is independent and therefore cannot effectively allocate power based on thread criticality to accelerate multi-threaded parallel applications, which are expected to be the primary workloads of many-core architectures. This paper presents a scalable power control solution for many-core microprocessors that is specifically designed to handle realistic workloads, i.e., a mixed group of single-threaded and multi-threaded applications. Our solution features a three-layer design. First, we adopt control theory to precisely control the power of the entire chip to its chip-level budget by adjusting the aggr...

• Type: Journal
• Year: 2011
• Where: ISCA
• Authors: Kai Ma, Xue Li, Ming Chen, Xiaorui Wang
• Keywords: Core Microprocessor, Hardware, ISCA 2011, Microprocessor Performance, Realistic Workloads