ISCA 2011 - PDF Preprint Papers

ISCA 2011 International Symposium on Computer Architecture

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ISCA
2011
IEEE

152views Hardware» more ISCA 2011»

CPPC: correctable parity protected cache

9 months 5 days ago

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Due to shrinking feature sizes processors are becoming more vulnerable to soft errors. Write-back caches are particularly vulnerable since they hold dirty data that do not exist i...

Mehrtash Manoochehri, Murali Annavaram, Michel Dub...

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Id	Views	Title	Status
1	152	CPPC: correctable parity protected cache	claim
2	108	Dark silicon and the end of multicore scaling	claim
3	94	Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs	claim
4	81	Increasing the effectiveness of directory caches by deactivating coherence for private memory blocks	claim
5	81	DBAR: an efficient routing algorithm to support multiple concurrent applications in networks-on-chip	claim
6	78	Prefetch-aware shared resource management for multi-core systems	claim
7	76	A case for heterogeneous on-chip interconnects for CMPs	claim
8	76	Virtualizing performance asymmetric multi-core systems	claim
9	74	Kilo-NOC: a heterogeneous network-on-chip architecture for scalability and service guarantees	claim
10	73	Scalable power control for many-core architectures running multi-threaded applications	claim
11	71	Sampling + DMR: practical and low-overhead permanent fault detection	claim
12	67	Moguls: a model to explore the memory hierarchy for bandwidth improvements	claim
13	67	Crafting a usable microkernel, processor, and I/O system with strict and provable information flow security	claim
14	64	Bypass and insertion algorithms for exclusive last-level caches	claim
15	64	FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template	claim
16	62	Power management of online data-intensive services	claim
17	61	FlexBulk: intelligently forming atomic blocks in blocked-execution multiprocessors to minimize squashes	claim
18	58	The impact of memory subsystem resource sharing on datacenter applications	claim
19	58	Rebound: scalable checkpointing for coherent shared memory	claim
20	58	TLSync: support for multiple fast barriers using on-chip transmission lines	claim
21	58	CRIB: consolidated rename, issue, and bypass	claim

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