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2003
IEEE

Scheduling Algorithms with Bus Bandwidth Considerations for SMPs

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Scheduling Algorithms with Bus Bandwidth Considerations for SMPs
The bus that connects processors to memory is known to be a major architectural bottleneck in SMPs. However, both software and scheduling policies for these systems generally focus on memory hierarchy optimizations and do not address the bus bandwidth limitations directly. In this paper, we first present experimental results which indicate that bus saturation can cause an up to almost three-fold slowdown to applications. Motivated by these results, we introduce two scheduling policies that take into account the bus bandwidth consumption of applications. The necessary information is provided by performance monitoring counters which are present in all modern processors. Our algorithms organize jobs so that processes with high-bandwidth and low-bandwidth demands are co-scheduled to improve bus bandwidth utilization without saturating the bus. We found that our scheduler is effective with applications of varying bandwidth requirements, from very low to close to the limit of saturation. W...
Christos D. Antonopoulos, Dimitrios S. Nikolopoulo
Added 04 Jul 2010
Updated 04 Jul 2010
Type Conference
Year 2003
Where ICPP
Authors Christos D. Antonopoulos, Dimitrios S. Nikolopoulos, Theodore S. Papatheodorou
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