An SDRAM-aware router for Networks-on-Chip

In this paper, we present an NoC (Networks-on-Chip) router with an SDRAM-aware flow control. Based on a priority-based arbitration, it schedules packets to improve memory utilization and reduce memory latency. Moreover, our multi-scheduling scheme performed by the multiple SDRAM-aware routers helps to achieve better SDRAM performance and save the hardware cost of NoC platform. Experimental results show that our SDRAMaware router improves memory latency by 18% and memory utilization by 4.9% on average with over 42% saving of gate count of the NoC platform with dual memory subsystem. Categories and Subject Descriptors C.2.1 [COMPUTER-COMMUNICATION NETWORKS]: Network Architecture and Design - Packet-switching networks. General Terms Algorithms, Performance, Design. Keywords Networks-on-Chip, router, flow control, memory

• Type: Conference
• Year: 2009
• Where: DAC
• Authors: Wooyoung Jang, David Z. Pan
• Keywords: DAC 2009, Design Automation, Dual Memory Subsystem, Memory Latency, Router Improves Memory