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DAC 2009 Design Automation Conference

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DAC
2009
ACM

132views Computer Architecture» more DAC 2009»

Efficient program scheduling for heterogeneous multi-core processors

2 years 2 months ago

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Heterogeneous multicore processors promise high execution efficiency under diverse workloads, and program scheduling is critical in exploiting this efficiency. This paper present...

Jian Chen, Lizy Kurian John

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Id	Views	Title	Status
1	132	Efficient program scheduling for heterogeneous multi-core processors	claim
2	93	Design automation for a 3DIC FFT processor for synthetic aperture radar: a case study	claim
3	87	PDRAM:a hybrid PRAM and DRAM main memory system	claim
4	81	PDRAM: a hybrid PRAM and DRAM main memory system	claim
5	75	Spectral techniques for high-resolution thermal characterization with limited sensor data
6	75	Throughput optimal task allocation under thermal constraints for multi-core processors	claim
7	74	GPU friendly fast Poisson solver for structured power grid network analysis	claim
8	64	A parameterized mask model for lithography simulation	claim
9	63	Human computing for EDA	claim
10	63	Context-sensitive timing analysis of Esterel programs	claim
11	62	Contract-based system-level composition of analog circuits	claim
12	62	SysCOLA: a framework for co-development of automotive software and system platform	claim
13	61	Event-driven gate-level simulation with GP-GPUs	claim
14	61	Matching-based minimum-cost spare cell selection for design changes	claim
15	61	On-line thermal aware dynamic voltage scaling for energy optimization with frequency/temperature dependency consideration	claim
16	60	An SDRAM-aware router for Networks-on-Chip	claim
17	57	Dynamic thermal management via architectural adaptation	claim
18	57	RegPlace: a high quality open-source placement framework for structured ASICs	claim
19	56	Vicis: a reliable network for unreliable silicon	claim
20	55	Improving testability and soft-error resilience through retiming	claim
21	55	PiCAP: a parallel and incremental capacitance extraction considering stochastic process variation	claim
22	55	Double patterning lithography friendly detailed routing with redundant via consideration	claim
23	54	Efficient SAT solving for non-clausal formulas using DPLL, graphs, and watched cuts	claim
24	53	A physical unclonable function defined using power distribution system equivalent resistance variations	claim
25	53	Provably good and practically efficient algorithms for CMP dummy fill	claim
26	53	WCET-aware register allocation based on graph coloring	claim
27	53	A real-time program trace compressor utilizing double move-to-front method	claim
28	53	Multicore parallel min-cost flow algorithm for CAD applications	claim
29	52	ILP-based pin-count aware design methodology for microfluidic biochips	claim
30	52	A DVS-based pipelined reconfigurable instruction memory	claim
31	51	The day Sherlock Holmes decided to do EDA	claim
32	51	Variational capacitance extraction of on-chip interconnects based on continuous surface model	claim
33	51	Fast vectorless power grid verification using an approximate inverse technique	claim
34	50	Way Stealing: cache-assisted automatic instruction set extensions	claim
35	50	A direct integral-equation solver of linear complexity for large-scale 3D capacitance and impedance extraction	claim
36	48	Nanoscale digital computation through percolation	claim
37	48	SRAM parametric failure analysis	claim
38	48	A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion	claim
39	48	Timing-driven optimization using lookahead logic circuits	claim
40	48	O-Router:an optical routing framework for low power on-chip silicon nano-photonic integration	claim
41	48	Internet-in-a-Box: emulating datacenter network architectures using FPGAs	claim
42	48	Information hiding for trusted system design	claim
43	48	Quality-driven synthesis of embedded multi-mode control systems	claim
44	47	Energy-aware error control coding for Flash memories	claim
45	47	Retiming and recycling for elastic systems with early evaluation	claim
46	47	BDD-based synthesis of reversible logic for large functions	claim
47	47	Computing bounds for fault tolerance using formal techniques	claim
48	47	Enabling adaptability through elastic clocks	claim
49	47	Reduction techniques for synchronous dataflow graphs	claim
50	46	A robust and efficient harmonic balance (HB) using direct solution of HB Jacobian	claim
51	46	GRIP: scalable 3D global routing using integer programming	claim
52	46	Selective wordline voltage boosting for caches to manage yield under process variations	claim
53	45	Power modeling of graphical user interfaces on OLED displays	claim
54	45	Finding deterministic solution from underdetermined equation:large-scale performance modeling by least angle regression	claim
55	45	Analysis and mitigation of process variation impacts on Power-Attack Tolerance	claim
56	45	O-Router: an optical routing framework for low power on-chip silicon nano-photonic integration	claim
57	45	Decoding nanowire arrays fabricated with the multi-spacer patterning technique	claim
58	45	Serial reconfigurable mismatch-tolerant clock distribution	claim
59	45	NoC topology synthesis for supporting shutdown of voltage islands in SoCs	claim
60	44	Debugging strategies for mere mortals	claim
61	44	Exploring serial vertical interconnects for 3D ICs	claim
62	44	Generating test programs to cover pipeline interactions	claim
63	44	Mode grouping for more effective generalized scheduling of dynamic dataflow applications	claim
64	43	Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications	claim
65	43	Heterogeneous code cache: using scratchpad and main memory in dynamic binary translators	claim
66	43	Optimal static WCET-aware scratchpad allocation of program code	claim
67	43	An adaptive scheduling and voltage/frequency selection algorithm for real-time energy harvesting systems	claim
68	42	Thermal-driven analog placement considering device matching	claim
69	42	Misleading performance claims in parallel computations	claim
70	42	Spare-cell-aware multilevel analytical placement	claim
71	42	Flip-chip routing with unified area-I/O pad assignments for package-board co-design	claim
72	42	Evaluating design trade-offs in customizable processors	claim
73	42	Improving STT MRAM storage density through smaller-than-worst-case transistor sizing	claim
74	42	A computing origami: folding streams in FPGAs	claim
75	42	On systematic illegal state identification for pseudo-functional testing	claim
76	41	Interconnection fabric design for tracing signals in post-silicon validation	claim
77	41	Speculation in elastic systems	claim
78	41	Carbon nanotube circuits in the presence of carbon nanotube density variations	claim
79	41	Process variation characterization of chip-level multiprocessors	claim
80	40	Statistical reliability analysis under process variation and aging effects	claim
81	40	Clock skew optimization via wiresizing for timing sign-off covering all process corners	claim
82	40	Beyond verification: leveraging formal for debugging	claim
83	40	NUDA: a non-uniform debugging architecture and non-intrusive race detection for many-core	claim
84	39	Handling complexities in modern large-scale mixed-size placement	claim
85	39	Endosymbiotic computing: enabling surrogate GUI and cyber-physical connectivity	claim
86	39	Non-intrusive dynamic application profiling for multitasked applications	claim
87	38	Non-cycle-accurate sequential equivalence checking	claim
88	38	Fault models for embedded-DRAM macros	claim
89	37	Efficient design-specific worst-case corner extraction for integrated circuits	claim
90	37	ARMS - automatic residue-minimization based sampling for multi-point modeling techniques	claim
91	36	Handling don't-care conditions in high-level synthesis and application for reducing initialized registers	claim
92	36	GPU-based parallelization for fast circuit optimization	claim
93	35	Xquasher: a tool for efficient computation of multiple linear expressions	claim
94	34	Thermal-aware data flow analysis	claim
95	34	Yield-driven iterative robust circuit optimization algorithm	claim
96	34	Exploiting "architecture for verification" to streamline the verification process	claim
97	34	Way Stealing:cache-assisted automatic instruction set extensions	claim
98	33	Online cache state dumping for processor debug	claim
99	33	Software-assisted hardware reliability: abstracting circuit-level challenges to the software stack	claim
100	33	Designing heterogeneous ECU networks via compact architecture encoding and hybrid timing analysis	claim
101	31	Accurate temperature estimation using noisy thermal sensors	claim

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