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DAC 2009 Design Automation Conference

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DAC
2009
ACM

274views Computer Architecture» more DAC 2009»

Spectral techniques for high-resolution thermal characterization with limited sensor data

14 years 5 months ago

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Elevated chip temperatures are true limiters to the scalability of computing systems. Excessive runtime thermal variations compromise the performance and reliability of integrated...

Ryan Cochran, Sherief Reda

posted by sreda

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Id	Views	Title	Status

1	274	Spectral techniques for high-resolution thermal characterization with limited sensor data
2	257	GPU friendly fast Poisson solver for structured power grid network analysis	claim
3	236	Efficient program scheduling for heterogeneous multi-core processors	claim
4	216	Design automation for a 3DIC FFT processor for synthetic aperture radar: a case study	claim
5	210	Throughput optimal task allocation under thermal constraints for multi-core processors	claim
6	207	Dynamic thermal management via architectural adaptation	claim
7	205	PDRAM:a hybrid PRAM and DRAM main memory system	claim
8	202	Computing bounds for fault tolerance using formal techniques	claim
9	192	Double patterning lithography friendly detailed routing with redundant via consideration	claim
10	188	Context-sensitive timing analysis of Esterel programs	claim
11	181	BDD-based synthesis of reversible logic for large functions	claim
12	179	PDRAM: a hybrid PRAM and DRAM main memory system	claim
13	174	A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion	claim
14	174	A direct integral-equation solver of linear complexity for large-scale 3D capacitance and impedance extraction	claim
15	174	A physical unclonable function defined using power distribution system equivalent resistance variations	claim
16	169	Heterogeneous code cache: using scratchpad and main memory in dynamic binary translators	claim
17	169	RegPlace: a high quality open-source placement framework for structured ASICs	claim
18	168	Analysis and mitigation of process variation impacts on Power-Attack Tolerance	claim
19	168	Serial reconfigurable mismatch-tolerant clock distribution	claim
20	165	Fast vectorless power grid verification using an approximate inverse technique	claim
21	160	A computing origami: folding streams in FPGAs	claim
22	158	Contract-based system-level composition of analog circuits	claim
23	158	On-line thermal aware dynamic voltage scaling for energy optimization with frequency/temperature dependency consideration	claim
24	157	Variational capacitance extraction of on-chip interconnects based on continuous surface model	claim
25	155	An adaptive scheduling and voltage/frequency selection algorithm for real-time energy harvesting systems	claim
26	154	Energy-aware error control coding for Flash memories	claim
27	153	Exploring serial vertical interconnects for 3D ICs	claim
28	152	NoC topology synthesis for supporting shutdown of voltage islands in SoCs	claim
29	151	Human computing for EDA	claim
30	151	Improving testability and soft-error resilience through retiming	claim
31	151	O-Router:an optical routing framework for low power on-chip silicon nano-photonic integration	claim
32	150	A DVS-based pipelined reconfigurable instruction memory	claim
33	150	O-Router: an optical routing framework for low power on-chip silicon nano-photonic integration	claim
34	149	Information hiding for trusted system design	claim
35	147	Event-driven gate-level simulation with GP-GPUs	claim
36	143	Enabling adaptability through elastic clocks	claim
37	142	Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications	claim
38	142	Vicis: a reliable network for unreliable silicon	claim
39	142	NUDA: a non-uniform debugging architecture and non-intrusive race detection for many-core	claim
40	141	Efficient SAT solving for non-clausal formulas using DPLL, graphs, and watched cuts	claim
41	140	GPU-based parallelization for fast circuit optimization	claim
42	139	Interconnection fabric design for tracing signals in post-silicon validation	claim
43	139	PiCAP: a parallel and incremental capacitance extraction considering stochastic process variation	claim
44	138	Spare-cell-aware multilevel analytical placement	claim
45	138	Way Stealing: cache-assisted automatic instruction set extensions	claim
46	137	Matching-based minimum-cost spare cell selection for design changes	claim
47	135	Designing heterogeneous ECU networks via compact architecture encoding and hybrid timing analysis	claim
48	133	Statistical reliability analysis under process variation and aging effects	claim
49	133	An SDRAM-aware router for Networks-on-Chip	claim
50	131	GRIP: scalable 3D global routing using integer programming	claim
51	129	Timing-driven optimization using lookahead logic circuits	claim
52	129	Finding deterministic solution from underdetermined equation:large-scale performance modeling by least angle regression	claim
53	127	Non-cycle-accurate sequential equivalence checking	claim
54	126	Debugging strategies for mere mortals	claim
55	125	Improving STT MRAM storage density through smaller-than-worst-case transistor sizing	claim
56	125	Decoding nanowire arrays fabricated with the multi-spacer patterning technique	claim
57	125	Clock skew optimization via wiresizing for timing sign-off covering all process corners	claim
58	125	A parameterized mask model for lithography simulation	claim
59	124	A real-time program trace compressor utilizing double move-to-front method	claim
60	123	ARMS - automatic residue-minimization based sampling for multi-point modeling techniques	claim
61	122	A robust and efficient harmonic balance (HB) using direct solution of HB Jacobian	claim
62	122	Selective wordline voltage boosting for caches to manage yield under process variations	claim
63	121	SysCOLA: a framework for co-development of automotive software and system platform	claim
64	120	Internet-in-a-Box: emulating datacenter network architectures using FPGAs	claim
65	119	Handling complexities in modern large-scale mixed-size placement	claim
66	119	Accurate temperature estimation using noisy thermal sensors	claim
67	118	Provably good and practically efficient algorithms for CMP dummy fill	claim
68	118	Retiming and recycling for elastic systems with early evaluation	claim
69	118	ILP-based pin-count aware design methodology for microfluidic biochips	claim
70	118	Evaluating design trade-offs in customizable processors	claim
71	118	Fault models for embedded-DRAM macros	claim
72	117	WCET-aware register allocation based on graph coloring	claim
73	116	Endosymbiotic computing: enabling surrogate GUI and cyber-physical connectivity	claim
74	116	Beyond verification: leveraging formal for debugging	claim
75	115	Carbon nanotube circuits in the presence of carbon nanotube density variations	claim
76	115	Optimal static WCET-aware scratchpad allocation of program code	claim
77	114	Power modeling of graphical user interfaces on OLED displays	claim
78	114	Generating test programs to cover pipeline interactions	claim
79	114	Multicore parallel min-cost flow algorithm for CAD applications	claim
80	113	Non-intrusive dynamic application profiling for multitasked applications	claim
81	112	The day Sherlock Holmes decided to do EDA	claim
82	112	Quality-driven synthesis of embedded multi-mode control systems	claim
83	111	Nanoscale digital computation through percolation	claim
84	111	SRAM parametric failure analysis	claim
85	110	Yield-driven iterative robust circuit optimization algorithm	claim
86	109	Exploiting "architecture for verification" to streamline the verification process	claim
87	109	Reduction techniques for synchronous dataflow graphs	claim
88	108	Process variation characterization of chip-level multiprocessors	claim
89	107	Thermal-driven analog placement considering device matching	claim
90	106	Way Stealing:cache-assisted automatic instruction set extensions	claim
91	106	On systematic illegal state identification for pseudo-functional testing	claim
92	106	Mode grouping for more effective generalized scheduling of dynamic dataflow applications	claim
93	105	Misleading performance claims in parallel computations	claim
94	104	Efficient design-specific worst-case corner extraction for integrated circuits	claim
95	103	Speculation in elastic systems	claim
96	100	Handling don't-care conditions in high-level synthesis and application for reducing initialized registers	claim
97	95	Flip-chip routing with unified area-I/O pad assignments for package-board co-design	claim
98	89	Xquasher: a tool for efficient computation of multiple linear expressions	claim
99	86	Thermal-aware data flow analysis	claim
100	81	Online cache state dumping for processor debug	claim
101	78	Software-assisted hardware reliability: abstracting circuit-level challenges to the software stack	claim

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