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1999
IEEE

Solving Satisfiability Problems on FPGAs using Experimental Unit Propagation Heuristic

9 years 5 months ago
Solving Satisfiability Problems on FPGAs using Experimental Unit Propagation Heuristic
This paperpresents new resultson anapproach for solvingsatisfiability problems (SAT), that is, creating a logic circuit that is specialized to solve each problem instance on Field Programmable Gate Arrays (FPGAs). This approach has become feasible due to recent advances in Reconfigurable Computing. We develop an algorithm that is suitable for a logic circuit implementation. This algorithm is basically equivalent to the Davis-Putnam procedure with Experimental Unit Propagation. The required hardware resources for the algorithm are less than those of MOM's heuristics.
Takayuki Suyama, Makoto Yokoo, Akira Nagoya
Added 03 Aug 2010
Updated 03 Aug 2010
Type Conference
Year 1999
Where IPPS
Authors Takayuki Suyama, Makoto Yokoo, Akira Nagoya
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