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SIGMOD
2011
ACM
179views Database» more  SIGMOD 2011»
8 years 4 months ago
How soccer players would do stream joins
In spite of the omnipresence of parallel (multi-core) systems, the predominant strategy to evaluate window-based stream joins is still strictly sequential, mostly just straightfor...
Jens Teubner, René Müller
FPL
2010
Springer
188views Hardware» more  FPL 2010»
8 years 11 months ago
SeqHive: A Reconfigurable Computer Cluster for Genome Re-sequencing
We demonstrate how Field Programmable Gate Arrays (FPGAs) may be used to address the computing challenges associated with assembling genome sequences from recent ultra-high-through...
Kristian Stevens, Henry Chen, Terry Filiba, Peter ...
CATA
2009
9 years 2 months ago
Built-in Self-Test for Memory Resources in Virtex-4 Field Programmable Gate Arrays
ABSTRACT: We present a Built-In Self-Test (BIST) approach for programmable embedded memories in Xilinx Virtex-4 Field Programmable Gate Arrays (FPGAs). The target resources are the...
Brooks R. Garrison, Daniel T. Milton, Charles E. S...
FPL
2008
Springer
98views Hardware» more  FPL 2008»
9 years 3 months ago
Comparing throughput and power consumption in both sequential and reconfigurable processors
Recent improvements in the memory capacity of Field Programmable Gate Arrays (FPGAs) have spurred interest in using the devices for arithmetic floating-point operations. However, ...
Kevin K. Liu, Charles B. Cameron, Antal A. Sarkady
DAC
2005
ACM
9 years 3 months ago
Exploring technology alternatives for nano-scale FPGA interconnects
Field Programmable Gate Arrays (FPGAs) are becoming increasingly popular. With their regular structures, they are particularly amenable to scaling to smaller technologies. On the ...
Aman Gayasen, Narayanan Vijaykrishnan, Mary Jane I...
FPL
2006
Springer
132views Hardware» more  FPL 2006»
9 years 5 months ago
Adaptive FPGAs: High-Level Architecture and a Synthesis Method
This paper presents preliminary work exploring adaptive field programmable gate arrays (AFPGAs). An AFPGA is adaptative in the sense that the functionality of subcircuits placed o...
Valavan Manohararajah, Stephen Dean Brown, Zvonko ...
AHS
2006
IEEE
127views Hardware» more  AHS 2006»
9 years 5 months ago
Using Hardware-Based Particle Swarm Method for Dynamic Optimization of Adaptive Array Antennas
The following article describes and discusses the suitability of the particle swarm optimization (PSO) for the employment with blind adaptation of the directional characteristic o...
Gabriella Kókai, Tonia Christ, Hans Holm Fr...
FPL
2009
Springer
179views Hardware» more  FPL 2009»
9 years 5 months ago
Building heterogeneous reconfigurable systems using threads
Field Programmable Gate Arrays (FPGAs) have long held the promise of allowing designers to create systems with performance levels close to custom circuits but with a software-like...
Jason Agron, David L. Andrews
FCCM
2009
IEEE
123views VLSI» more  FCCM 2009»
9 years 5 months ago
Scalable High Throughput and Power Efficient IP-Lookup on FPGA
Most high-speed Internet Protocol (IP) lookup implementations use tree traversal and pipelining. Due to the available on-chip memory and the number of I/O pins of Field Programmab...
Hoang Le, Viktor K. Prasanna
DFT
2007
IEEE
152views VLSI» more  DFT 2007»
9 years 5 months ago
TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs
This paper presents the adoption of the Triple Modular Redundancy coupled with the Partial Dynamic Reconfiguration of Field Programmable Gate Arrays to mitigate the effects of Sof...
Cristiana Bolchini, Antonio Miele, Marco D. Santam...
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