A Special-Purpose Architecture for Solving the Breakpoint Median Problem

Abstract--In this paper, we describe the design for a co-processor for whole-genome phylogenetic reconstruction. Our current design performs a parallelized breakpoint median computation, which is an expensive component of the overall application. When implemented on a field-programmable gate array (FPGA), our hardware breakpoint median achieves a maximum speedup of 1005 over software. When the coprocessor is used to accelerate the entire reconstruction procedure, we achieve a maximum application speedup of 417 . The results in this paper suggest that FPGA-based acceleration is a promising approach for computationally expensive phylogenetic problems, in spite of the fact that the involved algorithms are based on complex, control-dependent combinatorial optimization.

• Type: Journal
• Year: 2008
• Where: TVLSI
• Authors: Jason D. Bakos, Panormitis E. Elenis
• Keywords: Breakpoint Median Computation, Maximum Application Speedup, TVLSI 2008, Whole-genome Phylogenetic Reconstruction