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TVLSI
2008

Stack Sizing for Optimal Current Drivability in Subthreshold Circuits

8 years 5 months ago
Stack Sizing for Optimal Current Drivability in Subthreshold Circuits
Subthreshold circuit designs have been demonstrated to be a successful alternative when ultra-low power consumption is paramount. However, the characteristics of MOS transistors in the subthreshold region are significantly different from those in stronginversion. This presents new challenges in design optimization-particularly in complex gates with stacks of transistors. In this paper, we present a framework for choosing the optimal transistor stack sizing factors in terms of current drivability for subthreshold designs. We derive a closed-form solution for the correct sizing of transistors in a stack, both in relation to other transistors in the stack, and to a single device with equivalent current drivability. Simulation results show that our framework provides a performance benefit ranging up to more than 10% in certain critical paths.
John Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin S.
Added 16 Dec 2010
Updated 16 Dec 2010
Type Journal
Year 2008
Where TVLSI
Authors John Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim
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