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ISQED
2007
IEEE

Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS

10 years 5 months ago
Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS
Straining of silicon improves mobility of carriers resulting in speed enhancement for transistors in CMOS technology. Traditionally, silicon straining is applied in a similar ad-hoc manner to the whole die including logic and memory. Speed enhancement achieved for both NMOS and PMOS devices is desirable in logic circuits for performance enhancement because both PMOS and NMOS devices lie in critical delay paths. In SRAM cells however PMOS devices are not in the delay path and hence made small to minimize cell area and improve the write stability of the cell. Hence, speed enhancement of PMOS does not result in any reduction in cell access time and in fact it degrades the cell write ability. Hence, optimal method and amount of silicon straining for logic and memory should be different. In this paper, we propose an optimal straining solution for both logic and memory. Based on simulation results in a predictive 45nm process technology, the proposed straining solution enhances circuit perf...
Rajani Kuchipudi, Hamid Mahmoodi
Added 04 Jun 2010
Updated 04 Jun 2010
Type Conference
Year 2007
Where ISQED
Authors Rajani Kuchipudi, Hamid Mahmoodi
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