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ISCA
1995
IEEE

Streamlining Data Cache Access with Fast Address Calculation

11 years 11 months ago
Streamlining Data Cache Access with Fast Address Calculation
For many programs, especially integer codes, untolerated load instruction latencies account for a significant portion of total execution time. In this paper, we present the design and evaluation of a fast address generation mechanism capable of eliminating the delays caused by effective address calculation for many loads and stores. Our approach works by predicting early in the pipeline (part of) the effective address of a memory access and using this predicted address to speculatively access the data cache. If the prediction is correct, the cache access is overlapped with non-speculative effective address calculation. Otherwise, the cache is accessed again in the following cycle, this time using the correct effective address. The impact on the cache access critical path is minimal; the prediction circuitry adds only a single OR operation before cache access can commence. In addition, verification of the predicted effective address is completely decoupled from the cache access criti...
Todd M. Austin, Dionisios N. Pnevmatikatos, Gurind
Added 26 Aug 2010
Updated 26 Aug 2010
Type Conference
Year 1995
Where ISCA
Authors Todd M. Austin, Dionisios N. Pnevmatikatos, Gurindar S. Sohi
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