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CSREAESA
2004

Survey and Evaluation of Low-Power Full-Adder Cells

8 years 11 months ago
Survey and Evaluation of Low-Power Full-Adder Cells
In this paper, we survey various designs of low-power full-adder cells from conventional CMOS to really inventive XOR-based designs. We further describe simulation experiments that compare the surveyed full-adder cells. The experiments simulate all combinations of input transitions and consequently determine the delay and power consumption for the various full-adder cells. Moreover, the simulation results highlight the weaknesses and the strengths of the various full-adder cell designs.
Ahmed Sayed, Hussain Al-Asaad
Added 30 Oct 2010
Updated 30 Oct 2010
Type Conference
Year 2004
Where CSREAESA
Authors Ahmed Sayed, Hussain Al-Asaad
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