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ICCD
2007
IEEE

System level power estimation methodology with H.264 decoder prediction IP case study

9 years 6 days ago
System level power estimation methodology with H.264 decoder prediction IP case study
This paper presents a methodology to generate a hierarchy of power models for power estimation of custom hardware IP blocks, enabling a trade-off between power estimation accuracy, modeling effort and estimation speed. Our power estimation approach enables several novel system-level explorations - such as observing the effect of clock gating, and the effects of tweaking application-level parameters on system power with an estimation accuracy that is close to the gate-level. We implemented our methodology on an H.264 video decoder prediction IP case study, created power models, and evaluated the effects of varying design parameters (e.g., clock gating, I/P frame ratios, Quantization), allowing rapid system-level power exploration of these design parameters.
Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi,
Added 16 Mar 2010
Updated 16 Mar 2010
Type Conference
Year 2007
Where ICCD
Authors Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi, Nikil Dutt
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