A Thread and Data-Parallel MPEG-4 Video Encoder for a System-On-Chip Multiprocessor

We studied the dynamic instruction count reduction for a single-thread, vectorized and a multi-threaded, non-vectorized, MPEG-4 video encoder. Results indicate a maximum improvement of the order of 88% for 22 CPU contexts for the multi-threaded case whereas the single-thread, vectorized version demonstrates an 85% improvement for a vector register file length of 24 bytes, over the scalar case. We present VLSI macrocells of a vector accelerator implementing a subset of the MPEG-4 vector ISA and a 2-way, parametric, bus-based, cache coherent, SoC multi-processor.

• Type: Conference
• Year: 2005
• Where: ASAP
• Authors: Tom R. Jacobs, José L. Núñez-Yáñez
• Keywords: ASAP 2005, Distributed And Parallel Computing, Mpeg-4 Vector Isa, MPEG-4 Video Encoder, Vector Register File