Tolerating Transient Faults through an Instruction Reissue Mechanism

In this paper, we propose a fault-tolerant mechanism for microprocessors, which detects transient faults and recovers from them. There are two driving force to investigate fault-tolerant techniques for microprocessors. One is deep submicron fabrication technologies. Future semiconductor technologies could become more susceptible to alpha particles and other cosmic radiation. The other is increasing popularity of mobile platforms. Recently cell phones are used for applications which are critical to our nancial security, such as ight thicket reservation, mobile banking, and mobile trading. In such applications, it is expected that computer systems will always work correctly. From these observations, we propose the mechanism which is based on instruction reissue technique for incorrect data speculation recovery and utilizes time redundancy. We evaluate our proposal using a timing simulator and nd that it is more ecient than a space redundant technique based on a chip multiprocessor.

• Type: Conference
• Year: 2001
• Where: ISCAPDCS
• Authors: Toshinori Sato, Itsujiro Arita
• Keywords: Fault-tolerant Mechanism, Ight Thicket Reservation, ISCAPDCS 2001, ISCAPDCS 2007, Submicron Fabrication Technologies