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JOLPE
2006
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JOLPE 2006
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Transistor Sizing of Logic Gates to Maximize Input Delay Variability
13 years 5 months ago
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Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bush
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Added
13 Dec 2010
Updated
13 Dec 2010
Type
Journal
Year
2006
Where
JOLPE
Authors
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
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JOLPE 2006 Study Group
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