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ISQED
2009
IEEE

TuneLogic: Post-silicon tuning of dual-Vdd designs

10 years 11 months ago
TuneLogic: Post-silicon tuning of dual-Vdd designs
Modern CMOS manufacturing processes have significant variability, which necessitates guard banding to achieve reasonable yield. It is our thesis that variability should be addressed post-manufacturing. The fundamental contribution we make is a dual-Vdd design style, and associated CAD algorithms, wherein we assign supply voltages to logic based on post-manufacturing analysis rather than designing with nominal values and guard banding. We perform a detailed case study of a custom designed pipelined multiplier using realistic process data. Our results show that for comparable yield and target delay, we can achieve significantly less power than a single-Vdd supply. For example, to achieve 100% yield at same target delay, TuneLogic uses 23.6 pJ/multiply while a single-Vdd design uses 34.6 pJ/multiply. Keywords Process Variation, Tuning, Configurability, Yield, Delay
Stephen Bijansky, Sae Kyu Lee, Adnan Aziz
Added 19 May 2010
Updated 19 May 2010
Type Conference
Year 2009
Where ISQED
Authors Stephen Bijansky, Sae Kyu Lee, Adnan Aziz
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