Using Statistical and Symbolic Simulation for Microprocessor Performance Evaluation

As microprocessor designs continue to evolve, many optimizations reach a point of diminishing returns. We introduce HLS, a hybrid processor simulator which uses statistical models and symbolic execution to evaluate design alternatives. This simulation methodology enables quick and accurate generation of contour maps of the performance space spanned by design parameters. We validate the accuracy of HLS through correlation with existing cycle-by-cycle simulation techniques and current generation hardware. We demonstrate the power of HLS by exploring design spaces defined by two parameters: code properties and value prediction. These examples motivate how HLS can be used to set design goals and individual component performance targets.

• Type: Journal
• Year: 2002
• Where: JILP
• Authors: Mark Oskin, Frederic T. Chong, Matthew K. Farrens
• Keywords: Cycle-by-cycle Simulation Techniques, Design, Hybrid Processor Simulator, JILP 2002