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DSD
2005
IEEE

Validation of Embedded Systems Using Formal Method Aided Simulation

9 years 11 months ago
Validation of Embedded Systems Using Formal Method Aided Simulation
This paper proposes a validation approach, based on simulation, which addresses problems related to both state space explosion of formal methods and low coverage of informal methods. Formal methods, in particular model checking, are used to aid the simulation process in certain situations in order to boost coverage. The invocation frequency of the model checker is dynamically controlled by estimating certain parameters, based on statistics collected previously during the same validation session, in order to minimise verification time and at the same time achieve reasonable coverage. The approach has been demonstrated feasible by numerous experimental results.
Daniel Karlsson, Petru Eles, Zebo Peng
Added 24 Jun 2010
Updated 24 Jun 2010
Type Conference
Year 2005
Where DSD
Authors Daniel Karlsson, Petru Eles, Zebo Peng
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