Sciweavers

73 search results - page 1 / 15
» Validation of Embedded Systems Using Formal Method Aided Sim...
Sort
View
DSD
2005
IEEE
116views Hardware» more  DSD 2005»
13 years 10 months ago
Validation of Embedded Systems Using Formal Method Aided Simulation
This paper proposes a validation approach, based on simulation, which addresses problems related to both state space explosion of formal methods and low coverage of informal metho...
Daniel Karlsson, Petru Eles, Zebo Peng
HASE
2008
IEEE
13 years 4 months ago
Aiding Modular Design and Verification of Safety-Critical Time-Triggered Systems by Use of Executable Formal Specifications
Designing safety-critical systems is a complex process, and especially when the design is carried out at different f abstraction where the correctness of the design at one level i...
Kohei Sakurai, Péter Bokor, Neeraj Suri
MODELS
2009
Springer
13 years 11 months ago
Evaluating Context Descriptions and Property Definition Patterns for Software Formal Validation
A well known challenge in the formal methods domain is to improve their integration with practical engineering methods. In the context of embedded systems, model checking requires ...
Philippe Dhaussy, Pierre Yves Pillain, Stephen Cre...
DATE
2006
IEEE
125views Hardware» more  DATE 2006»
13 years 10 months ago
Combining simulation and formal methods for system-level performance analysis
Recent research on performance analysis for embedded systems shows a trend to formal compositional models and methods. These compositional methods can be used to determine the per...
Simon Künzli, Francesco Poletti, Luca Benini,...
ECRTS
1998
IEEE
13 years 8 months ago
Tool-supported hierarchical design of distributed real-time systems
In this paper we demonstrate the usage of a formal description technique for real-time systems called PLCAutomaton [4] by applying this method to a real-world case study. To this ...
Henning Dierks, Josef Tapken