Verification and Management of a Multimillion-Gate Embedded Core Design

Verification is one of the most critical and time-consuming tasks in today's design processes. This paper demonstrates the verification process of a 8.8 million gate design using HWsimulation and cycle simulation-based HW/SW-coverification. The main focuses are overall methodology, testbench management, the verification task itself and defect management. The chosen verification process was a real success: the quality of the designed hard- and software was increased and furthermore the time needed for integration and test of the design in the context of the overall system was greatly reduced. Keywords HW/SW-coverification, cycle-based simulation

• Type: Conference
• Year: 1999
• Where: DAC
• Authors: Johann Notbauer, Thomas W. Albrecht, Georg Niedrist, Stefan Rohringer
• Keywords: Chosen Verification Process, Computer Architecture, Cycle Simulation-based Hw/sw-coverification, DAC 1999, Verification Process