ICCAD
1996
IEEE
13 years 8 months ago
1996
IEEE
This paper presents a new framework for formal logic verification. What is depicted here is fundamentally different from previous approaches. In earlier approaches, the circuit is ...
DAC
1999
ACM
13 years 8 months ago
1999
ACM
Verification is one of the most critical and time-consuming tasks in today's design processes. This paper demonstrates the verification process of a 8.8 million gate design u...
DAC
2009
ACM
13 years 9 months ago
2009
ACM
A typical hardware development flow starts the verification process concurrently with RTL, but the overall schedule becomes limited by the effort required to complete all the nece...
DAC
2006
ACM
13 years 10 months ago
2006
ACM
Architectural decisions for DSP modules are often analyzed using high level C models. Such high-level explorations allow early examination of the algorithms and the architectural ...
DATE
2008
IEEE
13 years 10 months ago
2008
IEEE
Constant-coefficient multipliers are fundamental components in digital signal processing and arithmetic-based systems. Their verification, however, remains difficult and time-cons...