VRSync: Characterizing and eliminating synchronization-induced voltage emergencies in many-core processors

Power consumption is a primary concern for microprocessor designers. Lowering the supply voltage of processors is one of the most effective techniques for improving their energy efficiency. Unfortunately, low-voltage operation faces multiple challenges going forward. One such challenge is increased sensitivity to voltage fluctuations, which can trigger so-called “voltage emergencies” that can lead to errors. These fluctuations are caused by abrupt changes in power demand, triggered by processor activity variation as a function of workload. This paper examines the effects of voltage fluctuations on future many-core processors. With the increase in the number of cores in a chip, the effects of chip-wide activity fluctuation – such as that caused by global synchronization in multithreaded applications – overshadow the effects of core-level workload variability. Starting from this observation, we developed VRSync, a novel synchronization methodology that uses emergency-aware ...

• Type: Journal
• Year: 2012
• Where: ISCA
• Authors: Timothy N. Miller, Renji Thomas, Xiang Pan, Radu Teodorescu
• Keywords: Core Processors, Global Synchronization, Hardware, ISCA 2012, Microprocessor Designers