WiDGET: Wisconsin decoupled grid execution tiles

The recent paradigm shift to multi-core systems results in high system throughput within a specified power budget. However, future systems still require good single thread performance—no longer the predominant design priority—to mitigate sequential bottlenecks and/or to guarantee servicelevel agreements. Unfortunately, near saturation in voltage scaling necessitates a long-term alternative to dynamic voltage and frequency scaling. We propose an energy-proportional computing infrastructure, called WiDGET, that decouples thread context management from a sea of simple execution units (EUs). WiDGET’s decoupled design provides flexibility to alter resource allocation for a particular power-performance target while turning off unallocated resources. In other words, WiDGET enables dynamic customization of different combinations of small and/or powerful cores on a single chip, consuming power in proportion to the delivered performance. Over all SPEC CPU2006 benchmarks, WiDGET provides...

• Type: Conference
• Year: 2010
• Where: ISCA
• Authors: Yasuko Watanabe, John D. Davis, David A. Wood
• Keywords: Hardware, ISCA 2010, Mitigate Sequential Bottlenecks, Voltage Scaling Necessitates, WiDGET’s Decoupled Design