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CAMP
2005
IEEE
13 years 6 months ago
16-bit Floating Point Instructions for Embedded Multimedia Applications
— We have simulated the implementation of 16-bit floating point instructions on a Pentium4 and PowerPC G4 and G5 to evaluate the performance impact of these instructions in embed...
Lionel Lacassagne, Daniel Etiemble, S. A. Ould Kab...
ISCAS
2006
IEEE
107views Hardware» more  ISCAS 2006»
13 years 10 months ago
A versatile computation module for adaptable multimedia processors
—This paper describes a low cost, low power, versatile computation module that can be used as a coarse-grain building block in multimedia processors. The module, which has a data...
Yunan Xiang, R. Pettibon, Martin Margala
LCPC
2004
Springer
13 years 10 months ago
Speculative Subword Register Allocation in Embedded Processors
Abstract. Multimedia and network processing applications make extensive use of subword data. Since registers are capable of holding a full data word, when a subword variable is ass...
Bengu Li, Youtao Zhang, Rajiv Gupta
ARITH
2007
IEEE
13 years 11 months ago
A New Architecture For Multiple-Precision Floating-Point Multiply-Add Fused Unit Design
The floating-point multiply-add fused (MAF) unit sets a new trend in the processor design to speed up floatingpoint performance in scientific and multimedia applications. This ...
Libo Huang, Li Shen, Kui Dai, Zhiying Wang
DATE
2006
IEEE
118views Hardware» more  DATE 2006»
13 years 10 months ago
Design and implementation of a modular and portable IEEE 754 compliant floating-point unit
Multimedia and communication algorithms from embedded system domain often make extensive use of floating-point arithmetic. Due to the complexity and expense of the floating-poin...
Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Hei...